1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device in which a polycide wiring layer having a polysilicon film and a silicide film is formed as a wiring layer connected to impurity diffusion layers having opposite conductivity types, and a method of manufacturing the same.
2. Description of the Related Art
In recent years, demand for higher integration and higher-speed operation of semiconductor devices such as VLSI memories has arisen, and a technique of forming a polycide wiring layer having a two-layer structure of a polysilicon film and a silicide film, i.e., a compound of silicon (Si) and a refractory metal such as tungsten (W) has been proposed.
For example, Japanese Patent Laid-Open No. 4-277622 discloses a technique of electrically connecting an n-type diffusion layer and a p-type diffusion layer by using a polycide wiring layer having a silicide film of a refractory metal such as WSi in a semiconductor device such as a CMOS inverter having impurity diffusion layers of opposite conductivity types. In this technique, p- and n-type impurities are sequentially ion-implanted into the polysilicon film of the polycide wiring layer by using a photomask, and the polysilicon film is annealed to activate the impurities, thereby forming a polycide wiring layer constituted by p- and n-type portions connecting p- and n-type impurity diffusion layers. This technique is excellent because it enables relaxation of step coverage and reduction of the number of manufacturing processes. However, this technique has the following problem.
When annealing is performed at 800.degree. C. or more in processes after formation of the polycide wiring layer connecting the p- and n-type impurity diffusion layers, the p- or n-type impurity having a high diffusion coefficient and contained in the corresponding one of the two polysilicon films of opposite conductivity types moves in the silicide film and reaches the polysilicon film of a conductivity type opposite to that of the impurity, thus forming a p-n junction. This increases the resistance of the polycide wiring layer or causes an ohmic contact failure between the polysilicon film and the silicide film.
To cope with the above problem, a method is disclosed in, e.g., Japanese Patent Laid-Open No. 3-169022 or 3-101253, in which a polysilicon film is formed by arranging a p-type polycide wiring layer having a p-type polysilicon film connected to a p-type impurity diffusion layer parallel to an n-type polycide wiring layer having an n-type polysilicon film connected to an n-type impurity diffusion layer, and the p-type polysilicon film and the n-type polysilicon film are electrically connected, not directly, but through a low-resistance diffusion prevention film consisting of TiN. According to this technique, the two polycide wiring layers are rendered conductive through the diffusion prevention film having metallic properties. Additionally, impurity diffusion between the polysilicon films of the two polycide wiring layers can be prevented by the diffusion prevention film.
However, the diffusion prevention film of TiN has its crystal structure changed upon high-temperature annealing at a high temperature of 900.degree. C. or more and loses its barrier properties, resulting in damage to its function of preventing impurity diffusion. For this reason, restrictions are applied to annealing conditions after formation of the diffusion prevention film. When this technique is to be applied to manufacture, e.g., a DRAM whose memory cell has a COB (Capacitor Over Bitline) structure using a polycide wiring layer as a bit line of the DRAM, high-temperature annealing at 900.degree. C. or more is required to form an upper insulating interlayer or a dielectric film, so the diffusion prevention film of TiN cannot be used as a lower wiring layer. Instead, for example, a polycide wiring layer (n-type polycide wiring layer) is formed only on the n-type impurity diffusion layer side. When both the p- and n-type polycide wiring layers are to be positively formed, a diffusion prevention film is formed between each polycide wiring layer and a tungsten plug connected to each polycide wiring layer, as disclosed in Japanese Patent Laid-Open No. 3-169022. In this case, TiSiN is not formed because of a reaction at the interface between TiN and the polysilicon film. The crystal structure of TiN changes, and the barrier properties are lost.
When a diffusion prevention film is to be formed, as disclosed in Japanese Patent Laid-Open No. 3-169022, high-temperature annealing can be performed without posing any problems in the formation of a memory capacitor or an insulating interlayer covering the memory capacitor because the diffusion prevention film is formed after formation of the memory capacitor. However, since an upper insulating interlayer must be formed after formation of the diffusion prevention film, the problem of high-temperature annealing is still left unsolved.